View GS72108_4167251.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev: 1 .0 6 7/ 2000 1/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u 256k x 8 2 mb asynchronous sram 8, 10, 12 , 15 ns 3.3v v dd center v dd & v ss soj, tsop commercial temp industrial temp features ? fast access time: 8, 10 , 12 , 15 ns ? cmos low power operation: 150/125/110/90 ma at min. cycle time. ? single 3.3v 0.3v power supply ? all inputs and outputs are ttl compatible ? fully static operation ? industrial temperature option: -40 to 85c ? package line up j: 400mil, 36 pin soj package tp: 400mil, 44 pin tsop type ii package u: 6 mm x 8 mm fine pitch ball grid array package description the gs 7 2 1 08 is a high speed cmos static ram organized as 262,144 -words by 8 -bits. static design eliminates the need for exter- nal clocks or timing strobes. operating on a single 3.3v power supply and all inputs and outputs are ttl compatible. the gs 7 2 1 08 is avail- able in a 6x8 mm fine pitch bga package as well as in 400 mil soj and 400 mil tsop type-ii package s . pin descriptions fine pitch bga 256k x 8 bump configuration 6mm x 8mm, 0.75mm bump pitch top view soj 256k x 8 pin configuration symbol description a 0 to a 17 address input dq 1 to dq 8 data input/output ce chip enable input we write enable input oe output enable input v dd +3.3v power supply v ss ground nc no connect 1 2 3 4 5 6 a a 0 a 1 nc a 2 a 3 a 4 b dq 8 a 5 we a 6 a 7 dq 1 c dq 7 nc nc a 8 nc dq 2 d v ss nc nc nc nc v dd e v dd nc nc nc nc v ss f dq 6 nc nc a 17 nc dq 3 g dq 5 oe ce a 9 a 10 dq 4 h a 11 a 12 a 13 a 14 a 15 a 16 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 4 a 3 a 2 a 1 a 0 ce dq 1 dq 2 v dd v ss dq 3 dq 4 we a 17 a 16 a 15 nc a 5 a 6 a 7 a 8 oe dq 8 dq 7 v ss v dd dq 6 dq 5 a 9 a 10 a 11 a 12 36 pin 400mil soj 17 18 a 14 a 13 20 19 nc nc
rev: 1 .0 6 7/2000 2/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u tsop-ii 256k x 8 pin configuration 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 a 4 a 3 a 2 a 1 a 0 ce dq 1 dq 2 v dd v ss dq 3 dq 4 we nc a 5 a 6 a 7 a 8 oe dq 8 dq 7 v ss v dd dq 6 dq 5 a 10 a 11 a 12 nc 44 pin 400mil tsop ii 19 20 26 25 nc 21 22 nc nc 24 23 nc nc 1 2 nc nc 44 43 nc nc a 9 a 13 a 1 7 a 1 6 a 1 5 a 1 4 memory array row decoder column decoder address input buffer control i/o buffer a 0 ce we oe dq 1 a 17 block diagram dq 8
rev: 1 .0 6 7/2000 3/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u note: x: ?h? or ?l? note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation shall be restricted to recommen ded operating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. truth table ce oe we dq 1 to dq 8 v dd current h x x not selected isb 1 , isb 2 l l h read i dd l x l write l h h high z absolute maximum ratings parameter symbol rating unit supply voltage v dd -0.5 to +4.6 v input voltage v in -0.5 to v dd +0.5 ( 4.6v max.) v output voltage v out -0.5 to v dd +0.5 ( 4.6v max.) v allowable power dissipation pd 0.7 w storage temperature t stg -55 to 150 o c
rev: 1 .0 6 7/2000 4/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u note: 1. input overshoot voltage should be less than v dd +2v and not exceed 20ns. 2. input undershoot voltage should be greater than -2v and not exceed 20ns. notes: 1. tested at t a =25c, f=1mhz 2. these parameters are sampled and are not 100% tested recommended operating conditions parameter symbol min typ max unit supply voltage for - 10/12/15 v dd 3.0 3.3 3.6 v supply voltage for - 8 v dd 3.135 3.3 3.6 v input high voltage v ih 2.0 - v dd +0.3 v input low voltage v il -0.3 - 0.8 v ambient temperature, commercial range t ac 0 - 70 o c ambient temperature, industrial range t a i -40 - 85 o c capacitance parameter symbol test condition max unit input capacitance c in v in =0v 5 pf output capacitance c out v out =0v 7 pf dc i/o pin characteristics parameter symbol test conditions min max input leakage current i il v in = 0 to v dd -1ua 1ua output leakage current i lo output high z v out = 0 to v dd -1ua 1ua output high voltage v oh i oh = - 4ma 2.4 output low voltage v ol i lo = + 4ma 0.4v
rev: 1 .0 6 7/2000 5/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u ac test conditions power supply currents parameter symbol test conditions 0 to 70c -40 to 85c 8ns 10ns 12ns 15ns 10ns 12ns 15ns operating supply current i dd ce v il all other inputs 3 v ih or v il min. cycle time i out = 0 ma 150ma 125ma 110ma 90ma 135ma 120ma 100ma standby current i sb1 ce 3 v ih all other inputs 3 v ih or v il min. cycle time 55ma 50ma 45ma 40ma 60ma 55ma 50ma standby current i sb2 ce 3 v dd - 0.2v all other inputs 3 v dd - 0.2v or 0.2v 15ma 25ma dq vt=1.4v 50 w 30pf 1 dq 3.3v output load 1 output load 2 589 w 434 w 5pf 1 note: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted 3. output load 2 for t lz , t hz , t olz and t ohz . parameter conditions input high level v ih =2.4v input low level v il =0.4v input rise time tr=1v/ns input fall time tf=1v/ns input reference level 1.4v output reference level 1.4v output load fig. 1& 2
rev: 1 .0 6 7/2000 6/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u ac characteristics * these parameters are sampled and are not 100% tested read cycle 1: ce = oe = v il , we = v ih read cycle parameter symbol -8 -10 -12 -15 unit min max min max min max min max read cycle time t rc 8 --- 10 --- 12 --- 15 --- ns address access time t aa --- 8 --- 10 --- 12 --- 15 ns chip enable access time ( ce ) t ac --- 8 --- 10 --- 12 --- 15 ns output enable to output valid ( oe ) t oe --- 3.5 --- 4 --- 5 --- 6 ns output hold from address change t oh 3 --- 3 --- 3 --- 3 --- ns chip enable to output in low z ( ce ) t lz * 3 --- 3 --- 3 --- 3 --- ns output enable to output in low z ( oe ) t olz * 0 --- 0 --- 0 --- 0 --- ns chip disable to output in high z ( ce ) t hz * --- 4 --- 5 --- 6 --- 7 ns output disable to output in high z ( oe ) t ohz * --- 3.5 --- 4 --- 5 --- 6 ns t aa t oh t rc address data out previous data data valid
rev: 1 .0 6 7/2000 7/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u read cycle 2: we = v ih * these parameters are sampled and are not 100% tested write cycle parameter symbol -8 -10 -12 -15 unit min max min max min max min max write cycle time twc 8 --- 10 --- 12 --- 15 --- ns address valid to end of write taw 5.5 --- 7 --- 8 --- 10 --- ns chip enable to end of write tcw 5.5 --- 7 --- 8 --- 10 --- ns data set up time tdw 4 --- 5 --- 6 --- 7 --- ns data hold time tdh 0 --- 0 --- 0 --- 0 --- ns write pulse width twp 5.5 --- 7 --- 8 --- 10 --- ns address set up time tas 0 --- 0 --- 0 --- 0 --- ns write recovery time ( we ) twr 0 --- 0 --- 0 --- 0 --- ns write recovery time ( ce ) twr1 0 --- 0 --- 0 --- 0 --- ns output low z from end of write twlz * 3 --- 3 --- 3 --- 3 --- ns write to output in high z twhz * --- 3.5 --- 4 --- 5 --- 6 ns t aa t rc address t ac t lz t oe t olz ce oe data out t hz t ohz d a t a v a l i d high impedance
rev: 1 .0 6 7/2000 8/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u write cycle 1: we control write cycle 2: ce control t wc address ce we data in oe data out t aw t cw t as t wp t wr t dw t dh t wlz t whz d a t a v a l i d h i g h i m p e d a n c e t wc address ce we data in oe data out t aw t wp t as t cw t wr1 t dw t dh d a t a v a l i d h i g h i m p e d a n c e
rev: 1 .0 6 7/2000 9/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u 36 pin soj, 400 mil 1 e b1 d a 1 a 2 y e h e q c l g e detail a a b a note: 1. dimension d& e do not include interlead flash 2. dimension b1 does not include dambar protrusion / intrusion 3. controlling dimension: inches symbol dimension in inch dimension in mm min nom max min nom max a - - 0.146 - - 3.70 a1 0.026 - - 0.66 - - a2 0.105 0.110 0.115 2.67 2.80 2.92 b 0.013 0.017 0.021 0.33 0.43 0.53 b1 0.024 0.028 0.032 0.61 0.71 0.81 c 0.006 0.008 0.012 0.15 0.20 0.30 d 0.920 0.924 0.929 23.37 23.47 23.60 e 0.395 0.400 0.405 10.04 10.16 10.28 e - 0.05 - - 1.27 - h e 0.430 0.435 0.440 10.93 11.05 11.17 g e 0.354 0.366 0.378 9.00 9.30 9.60 l 0.082 - - 2.08 - - y - - 0.004 - - 0.10 q 0 o - 10 o 0 o - 10 o
rev: 1 .0 6 7/2000 10/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u 44 pin, 400 mil tsop-ii d 1 22 23 44 e b q a a 1 a 2 y c detail a e h e l l 1 a note: 1. dimension d& e do not include interlead flash 2. dimension b does not include dambar protrusion / intrusion 3. controlling dimension: mm symbol dimension in inch dimension in mm min nom max min nom max a - - 0.047 - - 1.20 a1 0.002 - - 0.05 - - a2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.01 0.014 0.018 0.25 0.35 0.45 c - 0.006 - - 0.15 - d 0.721 0.725 0.729 18.31 18.41 18.51 e 0.396 0.400 0.404 10.06 10.16 10.26 e - 0.031 - - 0.80 - h e 0.455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.020 0.024 0.40 0.50 0.60 l1 - 0.031 - - 0.80 - y - - 0.004 - - 0.10 q 0 o - 5 o 0 o - 5 o
rev: 1 .0 6 7/2000 11/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u 6mm x 8mm fine pitch bga c 5 . 2 5 0 . 7 5 ( t y p ) . 3 . 7 5 p i n a 1 i n d e x 6 5 4 3 2 1 a b d e f g h 0 . 2 2 0 . 0 5 1 . 2 0 ( m a x ) 0 . 3 6 ( t y p ) b a l l d i a . 0 . 3 5 p i t c h 0 . 7 5 d 0.10 p i n a 1 i n d e x b o t t o m v i e w t o p v i e w 6 . 0 0 0 . 1 0 8 . 0 0 0 . 1 0 u n i t s : m m
rev: 1 .0 6 7/2000 12/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u * customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. for example: gs 7 2 1 08 tp-8t ordering information part number * package access time temp. range status GS72108tp-8 400 mil tsop-ii 8 ns commercial GS72108tp-10 400 mil tsop-ii 10 ns commercial GS72108tp-12 400 mil tsop-ii 12 ns commercial GS72108tp-15 400 mil tsop-ii 15 ns commercial GS72108tp-8i 400 mil tsop-ii 8 ns industrial GS72108tp-10i 400 mil tsop-ii 10 ns industrial GS72108tp-12i 400 mil tsop-ii 12 ns industrial GS72108tp-15i 400 mil tsop-ii 15 ns industrial GS72108j-8 400 mil soj 8 ns commercial GS72108j-10 400 mil soj 10 ns commercial GS72108j-12 400 mil soj 12 ns commercial GS72108j-15 400 mil soj 15 ns commercial GS72108j-8i 400 mil soj 8 ns industrial GS72108j-10i 400 mil soj 10 ns industrial GS72108j-12i 400 mil soj 12 ns industrial GS72108j-15i 400 mil soj 15 ns industrial GS72108u-8 fine pitch bga 8 ns commercial GS72108u-10 fine pitch bga 10 ns commercial GS72108u-12 fine pitch bga 12 ns commercial GS72108u-15 fine pitch bga 15 ns commercial GS72108u-8i fine pitch bga 8 ns industrial GS72108u-10i fine pitch bga 10 ns industrial GS72108u-12i fine pitch bga 12 ns industrial GS72108u-15i fine pitch bga 15 ns industrial
rev: 1 .0 6 7/2000 13/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 2 1 08 tp /j /u revision history rev. code: old; new types of changes format or content page #/revisions/reason 72108 1.04d 5/1999 / 72108 1.05 1/ 2000 content 1. page 2/pins 16 - 20 and 26 - 30 on 44 pin tsop ii pin configuration/ correction. gs 7 2 1 08 rev 1 .05 10 /1999 1/ 2000 k ; rev 5 2/2000l format/content 1. gsi logo rev. 1.05; 72108_r1_06 content 1. corrected pinout for tsop-ii (a13 was moved from the right side to the left)

▲Up To Search▲

Price & Availability of GS72108

	To Download GS72108 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .